Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations

Author:

Sharma AnkurORCID,Chinnery David,Reimann TiagoORCID,Bhardwaj Sarvesh,Chu ChrisORCID

Funder

Mentor Graphics Corporation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. IR-Aware ECO Timing Optimization Using Reinforcement Learning;Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD;2024-09-09

2. CBi-GRU: Post-route timing path analysis method based on combined bidirectional GRU;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

3. A Variation-Aware Lagrangian Relaxation-Based Gate Sizing Framework for Timing Optimization;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08

4. A Novel Delay Calibration Method Considering Interaction between Cells and Wires;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04

5. Task-Based Parallel Programming for Gate Sizing;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-04

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