Latch-Based Performance Optimization for Field-Programmable Gate Arrays-Reference-Cited by-同舟云学术

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Latch-Based Performance Optimization for Field-Programmable Gate Arrays

Published:2013-05 Issue:5 Volume:32 Page:667-680
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Teng Bill,Anderson J. H.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/6504524/06504531.pdf?arnumber=6504531

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming;2021 31st International Conference on Field-Programmable Logic and Applications (FPL);2021-08

2. A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the Presence of Variations;IEEE Transactions on Circuits and Systems I: Regular Papers;2017-01

3. A novel PDWC-UCO algorithm-based buffer placement in FPGA architecture;International Journal of Circuit Theory and Applications;2016-10-24

4. Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-11

5. A Timing Error Mitigation Technique for High Performance Designs;2015 IEEE Computer Society Annual Symposium on VLSI;2015-07

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