Optimization of safe-operating-area using two peaks of body-current in submicron LDMOS transistors-Reference-Cited by-同舟云学术

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Optimization of safe-operating-area using two peaks of body-current in submicron LDMOS transistors

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Container-title:Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216)
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Author:

Lee S.K.,Kim C.J.,Kim J.H.,Choi Y.C.,Kang H.S.,Song C.S.

Publisher

Inst. Electr. Eng. Japan

Link

http://xplorestaging.ieee.org/ielx5/7438/20221/00934611.pdf?arnumber=934611

Cited by 18 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability;IEEE Access;2021

2. Optimization of Drain Extended MOS Devices for Reliability in High Switching applications;2020 5th IEEE International Conference on Emerging Electronics (ICEE);2020-11-26

3. Improved HCI of Embedded High Voltage EDNMOS in Advanced CMOS Process;2020 China Semiconductor Technology International Conference (CSTIC);2020-06-26

4. A Review on Hot-Carrier-Induced Degradation of Lateral DMOS Transistor;IEEE Transactions on Device and Materials Reliability;2018-06

5. Simulation and Analysis of InGaAs Power MOSFET Performances and Reliability;IEEE Transactions on Electron Devices;2011-01

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