Characterization of Interconnect Process Variation in CMOS Using Electrical Measurements and Field Solver

Author:

Lim Jun Jun,Johari Nor Adila,Rustagi Subhash C.,Arora Narain D.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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2. Variation-Aware Clock Path Timing Model in Near-Threshold Voltage;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08

3. Delay Impact on Process Variation of Interconnect throughout technology scaling;2022 19th International SoC Design Conference (ISOCC);2022-10-19

4. Stochastic Delay Characterization for Multicoupled RLC Interconnects Under Process Variations;Journal of Circuits, Systems and Computers;2019-08

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