Author:
Fuketa Hiroshi,Hirairi Koji,Yasufuku Tadashi,Takamiya Makoto,Nomura Masahiro,Shinohara Hirofumi,Sakurai Takayasu
Cited by
6 articles.
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1. Route Critical Nets in Upper Layers to Fix Timing Issues in Block Level CTS;2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2024-05-17
2. Analytical Stability Modeling for CMOS Latches in Low Voltage Operation;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2016
3. An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2015
4. Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-01
5. Extremely Low Power Digital and Analog Circuits;IEICE Transactions on Electronics;2014