An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Link
http://xplorestaging.ieee.org/ielx1/43/6568/00259947.pdf?arnumber=259947
Cited by 25 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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3. Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics;Journal of Electronic Testing;2019-12
4. Adapting an Implicit Path Delay Grading Method for Parallel Architectures;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2014-12
5. A novel parallel adaptation of an implicit path delay grading method;Proceedings of the 24th edition of the great lakes symposium on VLSI - GLSVLSI '14;2014
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