Pruning Binarized Neural Networks Enables Low-Latency, Low-Power FPGA-Based Handwritten Digit Classification-Reference-Cited by-同舟云学术

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Pruning Binarized Neural Networks Enables Low-Latency, Low-Power FPGA-Based Handwritten Digit Classification

Published:2023-09-25 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE High Performance Extreme Computing Conference (HPEC)
language:
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Author:

Payra Syamantak¹,Loke Gabriel²,Fink Yoel³,Steinmeyer Joseph D.⁴

Affiliation:

1. Stanford University (formerly Dept. of Electrical Engineering and Computer Science, Massachusetts Institute of Technology),Dept. of Electrical Engineering

2. Massachusetts Institute of Technology,Dept. of Materials Science and Engineering

3. Massachusetts Institute of Technology,Dept. of Materials Science and Engineering, Dept. of Electrical Engineering and Computer Science, and Institute for Soldier Nanotechnologies

4. Massachusetts Institute of Technology,Dept. of Electrical Enigneering and Computer Science

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10363430/10363422/10363509.pdf?arnumber=10363509

Reference66 articles.

1. FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review

2. Image Processing Using FPGAs

3. A COST-PERFORMANCE ANALYSIS OF EMBEDDED SYSTEMS FOR LOW AND MEDIUM-VOLUMES APPLICATIONS;Secrieru,2012

4. FPGA-Based Processor Acceleration for Image Processing Applications

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