Analysis of jitter due to power-supply noise in phase-locked loops-Reference-Cited by-同舟云学术

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Analysis of jitter due to power-supply noise in phase-locked loops

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Container-title:Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
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Author:

Heydari P.,Pedram M.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6878/18523/00852704.pdf?arnumber=852704

Cited by 25 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Method to Reduce Jitter Due to Power Noise by Optimizing Loop Filter in PLL Based Clock Source;2022 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC);2022-09-01

2. An Effective Global Approach for Assessment of Decoupling Capacitors on Mixed Planar and Transmission Line PDNs;IEEE Journal on Multiscale and Multiphysics Computational Techniques;2022

3. A new approach to increase the subsurface flaw detection capability of pulsed eddy current technique;Measurement;2018-11

4. A fast-locking low-jitter digitally-enhanced DLL dynamically controlled for loop-gain and stability;Analog Integrated Circuits and Signal Processing;2018-01-24

5. Concurrent Multi-Channel Crosstalk Jitter Characterization Using Coprime Period Channel Stimulus;IEEE Transactions on Circuits and Systems I: Regular Papers;2016-06

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