Frame mark selection, placement, design and simulation
Author:
Affiliation:
1. Beijing Superstring Academy of Memory Technology,Litho R&D Departments,Beijing,China
2. Changxin Memory Technologies Inc,Litho Departments,Beijing,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9971792/9972241/09972258.pdf?arnumber=9972258
Reference6 articles.
1. Wafer Alignment Mark manual;ASML Product Documentation ID 50195,0
2. Alignment method of self-aligned double patterning process
3. Overlay mark optimization using the KTD signal simulation system
4. Copper dual-damascene Alignment strategy recommendations;ASML Applications notes ID 95143,0
5. Performance study of new segmented overlay marks for advanced wafer processing
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1. Simulation study on the robustness of polar mark for incident light polarization states;2023 International Workshop on Advanced Patterning Solutions (IWAPS);2023-10-26
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