Linear-Exponential I-DS ADCs: Analysis, Limitations and Higher Order
Author:
Affiliation:
1. Institute of Microelectronics, University of Ulm,Ulm,Germany,D-89081
Funder
German Research Foundation under DFG
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10182215.pdf?arnumber=10182215
Reference14 articles.
1. Noise–Power Optimization of Incremental Data Converters
2. A single shot sigma delta analog to digital converter for multiplexed applications
3. A 550-$\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS
4. A 1.25MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDR
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1. DAC Element Mismatch Shaping Algorithms in Incremental Delta-Sigma ADCs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. Frequency-Domain Analysis of Reconfigured Incremental ΔΣ ADCs on the Example of the Exponential Phase;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-11
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