Homogeneous Ring Oscillator with Staggered Layout for Gate-level Delay Characterization-Reference-Cited by-同舟云学术

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Homogeneous Ring Oscillator with Staggered Layout for Gate-level Delay Characterization

Published:2022-03-21 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 34th International Conference on Microelectronic Test Structures (ICMTS)
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Author:

Udo Misaki¹,Islam Mahfuzul²,Onodera Hidetoshi³

Affiliation:

1. Kyoto University,Graduate School of Informatics,Yoshida-honmachi, Sakyo-ku,Kyoto 606-8501,JAPAN

2. Kyoto University,Graduate School of Engineering,Kyoto Daigaku Katsura, Nishikyo-ku,Kyoto 615-8510,JAPAN

3. Osaka Gakuin University,Faculty of Informatics,2-36-1 Kishibe-Minami,Suita 564-8511,JAPAN

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9898143/9898103/09898111.pdf?arnumber=9898111

Reference11 articles.

1. Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices

2. Impact of random telegraph noise on CMOS logic circuit reliability

3. Inhomogeneous Ring Oscillator for Within-Die Variability and RTN Characterization

4. Characterization of WID delay variability using RO-array test structures

5. Impact of random telegraph noise on CMOS logic delay uncertainty under low voltage operation

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