A 20 Gb/s CMOS Single-Chip 850 nm Optical Receiver
Author:
Affiliation:
1. High-Speed Circuits and Systems Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea
2. Post-Silicon Semiconductor Institute, Korea Institute of Science and Technology, Seoul, South Korea
Funder
Institute of Information and communications Technology Planning and Evaluation
Ministry of Science and ICT, South Korea
Development of Tbps/mm chiplet interface IP and silicon photonics technology for AI and vehicle SoC
IC Design Education Center (IDEC), Korea
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/50/10589311/10463111.pdf?arnumber=10463111
Reference17 articles.
1. A 56-Gb/s PAM-4 Transmitter/Receiver Chipset With Nonlinear FFE for VCSEL-Based Optical Links in 40-nm CMOS
2. Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects
3. Dynamic indoor free-space optical communication enabled by beam steering and beam shaping
4. An integrated 125-Gb/s optoelectronic receiver with a silicon avalanche photodetectorin standard SiGe BiCMOS technology
5. A 10-Gb/s −18.8 dBm Sensitivity 5.7 mW Fully-Integrated Optoelectronic Receiver With Avalanche Photodetector in 0.13-$\mu$ m CMOS
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