Convolutional Neural Network and Maxpooling Architecture on Zynq SoC FPGA-Reference-Cited by-同舟云学术

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Convolutional Neural Network and Maxpooling Architecture on Zynq SoC FPGA

Published:2019-10 Issue: Volume: Page:
ISSN:
Container-title:2019 International Symposium on Electronics and Smart Devices (ISESD)
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Author:

Bachtiar Y.A.,Adiono T.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8901968/8909400/08909510.pdf?arnumber=8909510

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. TensorRT Powered Model for Ultra-Fast Li-Ion Battery Capacity Prediction on Embedded Devices;Energies;2024-06-07

2. Analog Convolutional Operator Circuit for Low-Power Mixed-Signal CNN Processing Chip;Sensors;2023-12-04

3. A Low-complexity Max Unpooling Achitecture for CNNs;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24

4. Three-Dimensional-Slice-Super-Resolution-Net: A Fast Few Shooting Learning Model for 3D Super-Resolution Using Slice-Up and Slice-Reconstruction;Journal of Computing and Information Science in Engineering;2023-09-14

5. Robotics Framework for Object Tracking using FPGA with Novel Automatic Image Labelling;IEEE EUROCON 2023 - 20th International Conference on Smart Technologies;2023-07-06

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