Power Optimized Low Pass Digital FIR Filter Using Five Modular Redundancy and Parallel Adding Methods

Author:

Durgagopal R1,Rao D N2

Affiliation:

1. Joginpally BR Engineering College

2. Abhinav-Hitech College of Engineering

Publisher

IEEE

Reference11 articles.

1. -VLSI Implementation of Pipelined FIR Filterll International Journal of Innovative Research in Electrical;sharma;Electronics Instrumentation and Control Engineering,2013

2. -Folding and register minimization transformation on DSP filterI;joy;5th IEEE Uttar Pradesh Section Conference on Electrical and Computer Engineering (UPCON),2018

3. Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation

4. A design of low power and area efficient FIR filter using modified carry accumulator method;kannan;Turkish Journal of Computer and Mathematics Education,2021

5. Design and implementation of combined pipeling and parallel processing architecture FIR and IIR filter using VHDL. operators in FIR filter;bam;IEEE Trans Circuits Syst II Exp Briefs,2020

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