Impact of High-Level Synthesis on Reliability of Artificial Neural Network Hardware Accelerators

Author:

Traiola Marcello1ORCID,dos Santos Fernando Fernandes1ORCID,Rech Paolo2ORCID,Cazzaniga Carlo3ORCID,Sentieys Olivier1,Kritikakou Angeliki1ORCID

Affiliation:

1. Irisa, INRIA, CNRS, University of Rennes, Rennes, France

2. Department of Industrial Engineering, University of Trento, Trento, Italy

3. ISIS Facility, Rutherford Appleton Laboratory, Didcot, U.K.

Funder

European Union’s Horizon 2020 Research and Innovation Program under the Marie Sklodowska-Curie

Brittany Region and under the RadNext

Agence nationale de la recherche (ANR) Fault-aware timing behaviour for safety-critical multicore Systems

ANR RE-TRUSTING

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Reliability and Security of AI Hardware;2024 IEEE European Test Symposium (ETS);2024-05-20

2. Approximate Fault-Tolerant Neural Network Systems;2024 IEEE European Test Symposium (ETS);2024-05-20

3. Special Session: Reliability Assessment Recipes for DNN Accelerators;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22

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