An FPGA-Based ADC Using Multichain Merged Method-Reference-Cited by-同舟云学术

An FPGA-Based ADC Using Multichain Merged Method

Published:2024-03 Issue:3 Volume:71 Page:309-315
ISSN:0018-9499
Container-title:IEEE Transactions on Nuclear Science
language:
Short-container-title:IEEE Trans. Nucl. Sci.

Author:

Liu Songqing¹,Wu Zibing¹,Xu Weiwei¹,Hu Kun²^ORCID

Affiliation:

1. Shandong University, Shandong, Jinan, China

2. Key Laboratory of Particle Physics and Particle Irradiation (MOE), Institute of Frontier and Interdisciplinary Science, Shandong University, Qingdao, China

Funder

Shandong Excellent Young Scientists Fund Program

Key Technology Research and Development Program of Shandong Province

Natural Science Foundation of Shandong Province

Program of Qilu Young Scholars of Shandong University

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/23/10473595/10401996.pdf?arnumber=10401996

Reference24 articles.

1. An 8-bit CMOS 3.3-V 65-MHz digital-to-analog converter with a symmetric two-stage current cell matrix architecture

2. Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters

3. An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter

4. Using Multisines to Measure State-of-the-Art Analog-to-Digital Converters

5. Fast Digital Post-Processing Technique for Integral Nonlinearity Correction of Analog-to-Digital Converters: Validation on a 12-Bit Folding-and-Interpolating Analog-to-Digital Converter

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