A CMOS low-noise and low-power charge sampling integrated circuit for capacitive detector/sensor interfaces-Reference-Cited by-同舟云学术

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A CMOS low-noise and low-power charge sampling integrated circuit for capacitive detector/sensor interfaces

Published:1995 Issue:2 Volume:30 Page:110-119
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Tedja S.,Van der Speigel J.,Williams H.H.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx1/4/7992/00341737.pdf?arnumber=341737

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Note: A 102 dB dynamic-range charge-sampling readout for ionizing particle/radiation detectors based on an application-specific integrated circuit (ASIC);Review of Scientific Instruments;2018-02

3. Low noise and low power switched biased CSA with clocked reset and minimal PVT variation for APD based positron emission tomography;Analog Integrated Circuits and Signal Processing;2016-05-23

4. Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives;Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment;2014-11

5. A digitization scheme of sub-microampere current using a commercial comparator with hysteresis and FPGA-based wave union TDC;Journal of Instrumentation;2013-01-11

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