DTCO of Nanosheet and Forksheet Architectures: Exploring Dielectric Walls, Contacting Schemes, and Active Regions for Optimized RO Performance-Reference-Cited by-同舟云学术

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DTCO of Nanosheet and Forksheet Architectures: Exploring Dielectric Walls, Contacting Schemes, and Active Regions for Optimized RO Performance

Published:2024-03-03 Issue: Volume: Page:1-3
ISSN:
Container-title:2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
language:
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Author:

Gaddemane Gautam¹,Schuddinck Pieter¹,Bhuwalka Krishna²,Rzepa Gerhard³,Mirabelli Gioele¹,Matagne Philippe¹,Yakimets Dmitry²,Wu Hao²,Hellings Geert¹,Liu Changze²

Affiliation:

1. imec,Belgium

2. Huawei Technologies R&D,Belgium

3. Global TCAD Solutions,Austria

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10511270/10511310/10511609.pdf?arnumber=10511609

Reference9 articles.

1. 3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications

2. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

3. Novel forksheet device architecture as ultimate logic scaling device towards 2nm

4. PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Mandrel/spacer engineering-based patterning and metallization incorporating metal layer division and rigorously self-aligned vias and cuts (SAVC);Advanced Etch Technology and Process Integration for Nanopatterning XIII;2024-04-09

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