An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow-Reference-Cited by-同舟云学术

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An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow

Published:2024-05-19 Issue: Volume: Page:1-5
ISSN:
Container-title:2024 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Dai Zhenhui¹,Wang Jiawei¹,Zhong Yi¹,Feng Kunyu²,Zhao Cheng¹,Jiang Yuanyuan¹,Chen Peiyu¹,Wang Yuan¹,Yu Dunshan¹,Cui Xiaoxin¹

Affiliation:

1. Peking University,School of Integrated Circuits,Beijing,100871

2. Peking University,School of Software and Microelectronics,Beijing,102600

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10557746/10557828/10557877.pdf?arnumber=10557877

Reference9 articles.

1. 14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks

2. GoSPA: An Energy-efficient High-performance Globally Optimized SParse Convolutional Neural Network Accelerator

3. 31.3 A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators

4. Recurrent Residual Module for Fast Inference in Videos

5. Skip-Convolutions for Efficient Video Processing

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