Interface Trap Analysis in Multi-Fin FinFET Technology: a Crucial Reliability Issue in Digital Application
Author:
Affiliation:
1. Indian Institute of Technology,Roorkee
2. Graphic Era Deemed to be University,Dehradun,Uttarakhand
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558629.pdf?arnumber=10558629
Reference18 articles.
1. Device scaling limits of Si MOSFETs and their application dependencies
2. Considerations for Ultimate CMOS Scaling
3. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
4. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
5. FinFETs: from devices to architectures
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