A Closed-Loop Readout Circuit with Voltage Drop Mitigation for Emerging Resistive Technologies
Author:
Affiliation:
1. Imperial College London,Department of Electrical and Electronic Engineering,UK,SW7 2BT
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558625.pdf?arnumber=10558625
Reference14 articles.
1. Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme
2. High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications
3. A Nonvolatile AI-Edge Processor With SLC–MLC Hybrid ReRAM Compute-in-Memory Macro Using Current–Voltage-Hybrid Readout Scheme
4. Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation
5. Memristor Applications for Programmable Analog ICs
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