A 422.1 Mpixels/J Tile-based 4K Super Resolution Processor with Variable Bit Compression-Reference-Cited by-同舟云学术

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A 422.1 Mpixels/J Tile-based 4K Super Resolution Processor with Variable Bit Compression

Published:2024-05-19 Issue: Volume: Page:1-5
ISSN:
Container-title:2024 IEEE International Symposium on Circuits and Systems (ISCAS)
language:
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Author:

Jang Wuyoung¹,Lee Sangho¹,Jo Jinhoon¹,Jung Jueun¹,Han Donghyeon²,Lee Kyuho¹

Affiliation:

1. Ulsan National Institute of Science and Technology (UNIST),Graduate School of Artificial Intelligence,Department of Electrical Engineering,Ulsan,Republic of Korea

2. Massachusetts Institute of Technology (MIT),Department of Electrical Engineering and Computer Science,Cambridge,MA

Funder

National Research Foundation of Korea

IC Design Education Center

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558379.pdf?arnumber=10558379

Reference11 articles.

1. Video Super-Resolution With Convolutional Neural Networks

2. Learning a Deep Convolutional Network for Image Super-Resolution

3. Photo-Realistic Single Image Super-Resolution Using a Generative Adversarial Network

4. Accelerating the Super-Resolution Convolutional Neural Network

5. Gables: A Roofline Model for Mobile SoCs

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