High Throughput and Energy Efficient SHA-2 ASIC Design for Continuous Integrity Checking Applications
Author:
Affiliation:
1. University of Ioannina,Dept. of Computer Science and Engineering,Greece
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10173930/10173940/10174095.pdf?arnumber=10174095
Reference20 articles.
1. Application-oriented SHA-256 hardware design for low-cost RFID
2. A High-Performance Parallel Computation Hardware Architecture in ASIC of SHA-256 Hash
3. An FPGA Based SHA-256 Processor
4. Efficient single-chip implementation of SHA-384 and SHA-512
5. Secure hash standard validation system (shavs),0
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