Bus architecture synthesis for hardware-software co-design of deep submicron systems on chip
Author:
Publisher
IEEE Comput. Soc
Link
http://xplorestaging.ieee.org/ielx5/8790/27821/01240884.pdf?arnumber=1240884
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Synthesis of On-Chip Communication Architectures;On-Chip Communication Architectures;2008
2. Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision Processes;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2007-02
3. Applying stochastic modeling to bus arbitration for systems-on-chip;Integration;2007-02
4. Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2005-05
5. OSIRIS: automated synthesis of flat and hierarchical bus architectures for deep submicron systems on chip;IEEE Computer Society Annual Symposium on VLSI
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