Author:
Kondo M.,Okawara H.,Nakamura H.,Boku T.
Cited by
8 articles.
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1. A Versatile Data Cache for Trace Buffer Support;IEEE Transactions on Circuits and Systems I: Regular Papers;2014-11
2. On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches;ACM Transactions on Embedded Computing Systems;2014-03
3. Local Memory Design Space Exploration for High-Performance Computing;The Computer Journal;2010-03-23
4. Architecture and compiler co-optimization for high performance computing;International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
5. A New Memory Module for COTS-Based Personal Supercomputing;Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04)