Author:
Mishchenko A.,Brayton R.K.
Cited by
32 articles.
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1. Hardware Model Checking Algorithms and Techniques;Algorithms;2024-06-09
2. Using Formal Verification Methods for Optimization of Circuits Under External Constraints;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
3. LSTP: A Logic Synthesis Timing Predictor;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
4. Transduction Method for AIG Minimization;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
5. Garbled Circuits Reimagined: Logic Synthesis Unleashes Efficient Secure Computation;Cryptography;2023-11-23