Design as you see FIT: System-level soft error analysis of sequential circuits
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/4926138/5090609/05090770.pdf?arnumber=5090770
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Towards Evaluating SEU Type Soft Error Effects with Graph Attention Network;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
2. DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-10
3. An Improved Multi-Objective Optimization Framework for Soft-Error Immune Circuits;2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2022-11-11
4. Multi-objective Optimization Hardening Design for Multiplier Circuit;2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT);2022-10-25
5. Synergistic Effect of BTI and Process Variations on the Soft Error Rate Estimation in Digital Circuits;IEEE Access;2022
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