Author:
Chatterjee D.,DeOrio A.,Bertacco V.
Cited by
9 articles.
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1. General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09
2. Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism;Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 4;2023-03-25
3. Simulating Power Scheduling at Scale;Proceedings of the 5th International Workshop on Energy Efficient Supercomputing;2017-11-12
4. Power Analysis and Optimization from Circuitto Register-Transfer Levels;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14
5. A GPU-Based Fault Simulator for Small-Delay Faults;Advanced Materials Research;2013-08