Author:
Frere S.F.,Desoete B.,Rhayem J.,Anser M.,Walton A.J.
Cited by
2 articles.
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1. Parasitic
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Aware Delay Corner Model for Sub-10-nm Logic Circuit Design;IEEE Transactions on Electron Devices;2019-01
2. Statistical Compact Model Extraction: A Neural Network Approach;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2012-12