Malware Identification in Advanced Interconnects on SOC
Author:
Affiliation:
1. GRIET,Dept of ECE,Hyderabad
2. School of engineering, VIT,Chennai
3. Sona college of technology,Dept of IT,Salem
4. KITS,Dept of ECE,Coimbatore
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9850966/9850971/09851146.pdf?arnumber=9851146
Reference13 articles.
1. Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
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4. Maximal Length test pattern generation for the cryptography application;patnala;Elsevier materialstoday,0
5. Evaluating security requirements in a general-purpose processor by combining assertion checkers with code coverage
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