Power Side-Channel Attacks and Countermeasures on Computation-in-Memory Architectures and Technologies

Author:

Sapui Brojogopal1,Krautter Jonas1,Mayahinia Mahta1,Jafari Atousa1,Gnad Dennis1,Meschkov Sergej1,Tahoori Mehdi B.1

Affiliation:

1. Karlsruhe Institute of Technology (KIT),Institute of Computer Engineering,Karlsruhe,Germany

Publisher

IEEE

Reference22 articles.

1. {DRAMA}: Exploiting {DRAM} addressing for {Cross-CPU} attacks;pessl;Usenix Security ‘16,2016

2. A testing methodology for side-channel resistance validation;goodwill;NIST NIAT,2011

3. Secure STT-MRAM bit-cell design resilient to differential power analysis attacks;dodo;IEEE TVLSI systems,2019

4. Comprehensive Study of Side-Channel Attack on Emerging Non-Volatile Memories

5. A side-channel and fault-attack resistant AES circuit working on duplicated complemented values

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Side-Channel Attack with Fault Analysis on Memristor-based Computation-in-Memory;2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS);2024-07-03

2. Power Side-Channel Analysis and Mitigation for Neural Network Accelerators based on Memristive Crossbars;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

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