Design Patterns for Code Reuse in HLS Packet Processing Pipelines

Author:

Eran Haggai,Zeno Lior,Istvan Zsolt,Silberstein Mark

Publisher

IEEE

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. HAL: Hardware-assisted Load Balancing for Energy-efficient SNIC-Host Cooperative Computing;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

2. High-Level Synthesis of Geant4 Particle Transport Application for FPGA;2022 25th Euromicro Conference on Digital System Design (DSD);2022-08

3. FLOWER: A comprehensive dataflow compiler for high-level synthesis;2021 International Conference on Field-Programmable Technology (ICFPT);2021-12-06

4. Transformations of High-Level Synthesis Codes for High-Performance Computing;IEEE Transactions on Parallel and Distributed Systems;2021-05-01

5. Fine-Grained Pipeline Parallelization for Network Function Programs;2021 IEEE/ACM International Symposium on Code Generation and Optimization (CGO);2021-02-27

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