A Novel Dead-Time Elimination Method for Voltage Source Multilevel Converters
Author:
Affiliation:
1. National Key Laboratory of Science and Technology on Vessel Integrated Power System, Naval University of Engineering, Wuhan, China
Funder
National Natural Science Foundation of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/63/9952160/09925653.pdf?arnumber=9925653
Reference40 articles.
1. Carrier based three-level PWM for improving flying capacitor balancing of Nested Neutral-Point-Clamped (NNPC) converter
2. A Space Virtual-Vector Modulation With Voltage Balance Control for Nested Neutral-Point Clamped Converter Under Low Output Frequency Conditions
3. Single-Phase Frequency-Locked Loops: A Comprehensive Review
4. An Improved Second-Order Generalized Integrator Based Quadrature Signal Generator
5. A Switching Sequence Optimization Method (SSOM) to Eliminate the Dead-Time Unexpected Output Levels for Four-Level Nested Neutral Point Clamped Converter
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