Automatic Digital Optimization Design of Synchronous Rectification Buck Converter-Reference-Cited by-同舟云学术

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Automatic Digital Optimization Design of Synchronous Rectification Buck Converter

Published:2024-10 Issue:10 Volume:39 Page:13429-13441
ISSN:0885-8993
Container-title:IEEE Transactions on Power Electronics
language:
Short-container-title:IEEE Trans. Power Electron.

Author:

Dong Shufan¹^ORCID,Luo Quanming¹^ORCID,Wei Mengjia¹^ORCID,Lai Guolin¹^ORCID,Chen Jian²^ORCID,Sun Pengju¹^ORCID,Du Xiong¹^ORCID

Affiliation:

1. State Key Laboratory of Power Transmission Equipment and System Security and New Technology, School of Electrical Engineering, Chongqing University, Chongqing, China

2. School of Electrical Engineering, Southwest Jiaotong University, Chengdu, China

Funder

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/63/10659244/10606052.pdf?arnumber=10606052

Reference25 articles.

1. The Ripple Cancellation Technique Applied to a Synchronous Buck Converter to Achieve a Very High Bandwidth and Very High Efficiency Envelope Amplifier

2. Buck Converter With Load Adaptive Losses and 256x Sub-mW Load Transient Response Time of 0.8 ms Using Synchronous Control

3. Current-Limited Suboptimal Sliding Mode Control for Voltage-Regulated Synchronous Buck Converters

4. Proposed Switching Losses Model for Integrated Point-of-Load Synchronous Buck Converters

5. Two-Stage 48 V-12 V/6 V-1.8 V Voltage Regulator Module With Dynamic Bus Voltage Control for Light-Load Efficiency Improvement

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