A Capacitorless External-Clock-Free Fully Synthesizable Digital LDO With Time-Based Load-State Decision and Asynchronous Recovery-Reference-Cited by-同舟云学术

A Capacitorless External-Clock-Free Fully Synthesizable Digital LDO With Time-Based Load-State Decision and Asynchronous Recovery

Published:2024-01 Issue:1 Volume:39 Page:985-997
ISSN:0885-8993
Container-title:IEEE Transactions on Power Electronics
language:
Short-container-title:IEEE Trans. Power Electron.

Author:

Oh Jonghyun¹^ORCID,Song Yoonho²^ORCID,Hwang Young-Ha³^ORCID,Park Jun-Eun⁴^ORCID,Seok Mingoo⁵^ORCID,Jeong Deog-Kyoon²^ORCID

Affiliation:

1. Custom Circuit Group, Apple, Cupertino, CA, USA

2. Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea

3. School of Electronic Engineering, Department of Intelligent Semiconductors, Soongsil University, Seoul, South Korea

4. Department of Electrical and Computer Engineering, College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South Korea

5. Department of Electrical Engineering, Columbia University, New York, NY, USA

Funder

National Research Foundation of Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/63/10339150/10268501.pdf?arnumber=10268501

Reference29 articles.

1. A 10 nA Ultra-Low Quiescent Current and 60 ns Fast Transient Response Low-Dropout Regulator for Internet-of-Things

2. An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator

3. A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR and High Efficiency

4. A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns

5. An NMOS Digital LDO With NAND-Based Analog-Assisted Loop in 28-nm CMOS

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1. An Ultrawide Load-Range Fast-Transient Output Capacitor-Less Digital LDO With Adaptive Gate Modulation and Droop Detection;IEEE Solid-State Circuits Letters;2024

2. A 2.5-A 3-ns-Response-Time Calibration-Free Hybrid LDO Using Scalable Self-Clocked Stochastic Flash-ADC for In-Loop Quantization;IEEE Transactions on Circuits and Systems I: Regular Papers;2024