Author:
Huang C.,Yang Y.,Prince J.L.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Cited by
9 articles.
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1. Simultaneous switching noise reduction by resonant clock distribution networks;Integration;2014-03
2. A Method to Derive SSO Design Rule Considering Jitter Constraint;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2006-04-01
3. Influence of a floating plane on effective ground plane inductance in multilayer and coplanar packages;IEEE Transactions on Advanced Packaging;1999-05
4. Techniques and circuits for reducing switching noise;Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs;1999
5. Substrate biasing and noise coupling;Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs;1999