Author:
Chung-Yuan Tsao ,Shiue R.Y.,Ting C.C.,Huang Y.S.,Lin Y.C.,Yue J.T.
Cited by
6 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Wafer Test Methods to Improve Semiconductor Die Reliability;IEEE Design & Test of Computers;2008-11
2. A Prevenient Voltage Stress Test Method for High Density Memory;4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008);2008-01
3. Real Impact of Dynamic Operation Stress During Burn-In on DRAM Retention Time;IEEE Transactions on Electron Devices;2004-04
4. Investigation of wafer level burn-in to SoC memory: 1TRAM;2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.
5. DRAM reliability characterization by using dynamic operation stress in wafer burn-in mode;2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.