The influence of process and design of subcollectors on the ESD robustness of ESD structures and silicon germanium heterojunction bipolar transistors in a BiCMOS SiGe technology
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/8520/26927/01197772.pdf?arnumber=1197772
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Effects of Collector Profile on the SET Response of 130-nm High-Speed and High-Breakdown SiGe HBTs;IEEE Transactions on Nuclear Science;2023
2. High-<tex>$Q$</tex>Electrostatic Discharge (ESD) Protection Devices for Use at Radio Frequency (RF) and Broad-band I/O Pins;IEEE Transactions on Electron Devices;2005-07
3. A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I—ESD;Microelectronics Reliability;2005-02
4. An automated design system methodology and strategy for electrostatic discharge protection circuits in RF CMOS and BiCMOS silicon germanium technology;Journal of Electrostatics;2003-10
5. The influence of heavily doped buried layer implants on electrostatic discharge (ESD), latchup, and a silicon germanium heterojunction bipolar transistor in a BiCMOS SiGe technology;2004 IEEE International Reliability Physics Symposium. Proceedings
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