Effect of layout orientation on the performance and reliabiltiy of high voltage N-LDMOS in standard submicron logic STI CMOS process-Reference-Cited by-同舟云学术

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Effect of layout orientation on the performance and reliabiltiy of high voltage N-LDMOS in standard submicron logic STI CMOS process

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Container-title:2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.
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Author:

Bin Wang ,Hoc Nguyen ,Mavoori J.,Horch A.,Yanjun Ma ,Humes T.,Paulsen R.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/9994/32106/01493189.pdf?arnumber=1493189

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate;International Journal of RF and Microwave Computer-Aided Engineering;2021-08-10

2. Predictive Compact Modeling of Abnormal LDMOS Characteristics Due to Overlap-Length Modification;2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD);2020-09-23

3. Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2013-05

4. Physics, Technology, and Modeling of Complementary Asymmetric MOSFETs;IEEE Transactions on Electron Devices;2010-10

5. Development of Low-Vgs N-LDMOS Structure with Double Gate Oxide for Improving Rsp;Transactions on Electrical and Electronic Materials;2009-12-31

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