Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Signal Processing
Cited by
7 articles.
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1. Leveraging MLIR for Efficient Irregular-Shaped CGRA Overlay Design: (PhD Forum Paper);2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2024-07-24
2. An Architectural Template for FPGA Overlays Targeting Data Flow Applications;2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2024-05-27
3. Dynamic and Partial Reconfiguration of FPGAs;Handbook of Computer Architecture;2024
4. Investigating the Impact of Non-Volatile Memories on Energy-Efficiency of Coarse-Grained Reconfigurable Architectures;2023 26th Euromicro Conference on Digital System Design (DSD);2023-09-06
5. SPADES: A Productive Design Flow for Versal Programmable Logic;2023 33rd International Conference on Field-Programmable Logic and Applications (FPL);2023-09-04