A 2+1 Hybrid Incremental MASH Converter-Reference-Cited by-同舟云学术

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A 2+1 Hybrid Incremental MASH Converter

Published:2022-06-12 Issue: Volume: Page:
ISSN:
Container-title:2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)
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Author:

Colucci Antonio¹,Rigo Massimo²,Fiocchi Carlo³,Malcovati Piero¹,Bonizzoni Edoardo¹

Affiliation:

1. University of Pavia,Department of Electrical, Computer, and Biomedical Engineering,Pavia,ITALY

2. ams OSRAM Group,Garching,GERMANY

3. ams OSRAM Group,Pavia,ITALY

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9816371/9816743/09816778.pdf?arnumber=9816778

Reference13 articles.

1. A high-resolution low-power and multi-bit incremental converter with smart-DEM

2. Robust Continuous-Time MASH Delta Sigma Modulator

3. A 15-MHz Bandwidth 1-0 MASH $\Sigma \Delta $ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR

4. Third-order ?? modulator with 61-dB SNR and 6-MHz bandwidth consuming 6 mW;bonizzoni;Proc IEEE European Solid-State Circuits Conf (ESSCIRC),2008

5. A Low-Power 22-bit Incremental ADC

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