On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks-Reference-Cited by-同舟云学术

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On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks

Published:2015-10 Issue: Volume: Page:
ISSN:
Container-title:2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)
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Author:

Backer Jerry,Hely David,Karri Ramesh

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7304347/7315124/07315131.pdf?arnumber=7315131

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Technique for detecting hardware-based Trojans using a convolutional neural network;International Journal of Information and Computer Security;2024

2. IP-Tag: Tag-Based Runtime 3PIP Hardware Trojan Detection in SoC Platforms;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-01

3. Special Session: Closed Chassis Platform Debug of Compute Systems using the Functional Ubiquitous USB Type-C Receptacle;2022 IEEE 40th VLSI Test Symposium (VTS);2022-04-25

4. A Move Towards a Hardware Patch;Security Policy in System-on-Chip Designs;2018-10-10

5. Exploiting Design-for-Debug in SoC Security Policy Architecture;Security Policy in System-on-Chip Designs;2018-10-10

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