A 4.6pJ/b 64Gb/s Transceiver Enabling PCIe 6.0 and CXL 3.0 in Intel 3 CMOS Technology-Reference-Cited by-同舟云学术

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A 4.6pJ/b 64Gb/s Transceiver Enabling PCIe 6.0 and CXL 3.0 in Intel 3 CMOS Technology

Published:2024-06-16 Issue: Volume: Page:1-2
ISSN:
Container-title:2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
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Author:

Choi Dong-Myung¹,Dong Yikui¹,Nicholson Roan¹,Liu Frank¹,Jia Wenyan¹,Levin Vadim¹,He Mike¹,Pradhan Sameer¹,Du Jieqiong¹,De Vita Michael¹,Tran Amanda¹,Navid Reza¹,Iyer Sitaraman¹,Song Rui¹

Affiliation:

1. Intel,Santa Clara,CA,USA,95054

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10631290/10631310/10631462.pdf?arnumber=10631462

Reference3 articles.

1. A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET

2. Rotary traveling-wave oscillator arrays: a new clock technology

3. A 1–58.125 Gb/s, 5-33dB IL Multi-Protocol Ethernet-Compliant Analog PAM-4 Receiver with 16 DFE Taps in 10nm;Bahram;ISSCC,2022

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