The semantic challenge of Verilog HDL-Reference-Cited by-同舟云学术

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The semantic challenge of Verilog HDL

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Container-title:Proceedings of Tenth Annual IEEE Symposium on Logic in Computer Science
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Author:

Gordon M.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx3/3961/11443/00523251.pdf?arnumber=523251

Cited by 46 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog;Proceedings of the ACM on Programming Languages;2023-10-16

2. Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units;Microprocessors and Microsystems;2023-06

3. A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block;Engineering Research Express;2023-03-01

4. A small, but important, concurrency problem in Verilog's semantics? (Work in progress);2022 20th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE);2022-10-13

5. Generating circuits with generators;Proceedings of the ACM on Programming Languages;2022-08-29

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