Impact of epi facets on deep submicron elevated source/drain MOSFET characteristics
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx4/16/14932/00678583.pdf?arnumber=678583
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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3. Technique for Large Elevation of Source/Drain Using Implantation Mediated Selective Etching;Electrochemical and Solid-State Letters;2003
4. A Technique for Source/Drain Elevation using Implantation Mediated Selective Etching;MRS Proceedings;2003
5. Optimization of process conditions of selective epitaxial growth for elevated source/drain CMOS transistor;Journal of Crystal Growth;2002-08
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