Author:
Bellas N.,Hajj I.,Polychronopoulos C.,Stamoulis G.
Cited by
22 articles.
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1. CASINO Core Microarchitecture: Generating Out-of-Order Schedules Using Cascaded In-Order Scheduling Windows;2020 IEEE International Symposium on High Performance Computer Architecture (HPCA);2020-02
2. OTR: A Fine-Grained Dynamic Power Scaling Pipeline Based on Trace;2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC);2017-12
3. An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques;Advances in Computers;2015
4. DLIC;ACM Transactions on Embedded Computing Systems;2013-08
5. Adaptive loop caching using lightweight runtime control flow analysis;ACM Transactions on Embedded Computing Systems;2013-03