Technology Scaling and Device Design for 350 GHz RF Performance in a 45nm Bulk CMOS Process
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4339664/4339665/04339725.pdf?arnumber=4339725
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. mm-Wave CMOS Device Optimization Design for Super-400 GHz fMAX with Impact of Technology Scaling and Layout Dependent Effects;2023 Asia-Pacific Microwave Conference (APMC);2023-12-05
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4. Performance Enhancement and Signal Distortion Analysis of Virtually Doped Nanotube Tunnel FET with Embedded Ferroelectric Gate Oxide;Silicon;2021-01-06
5. A comprehensive analysis of nanoscale single- and multi-gate MOSFETs;Microelectronics Journal;2016-06
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