A fast wafer-level screening test for VLSI metallization-Reference-Cited by-同舟云学术

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A fast wafer-level screening test for VLSI metallization

Published:1993-06 Issue:6 Volume:14 Page:307-309
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Menon S.S.,Fu K.-Y.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx1/55/5622/00215207.pdf?arnumber=215207

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-the-Fly Etching Process Modification;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2015

2. Isothermal test as a WLR monitor for Cu interconnects;SPIE Proceedings;2000-08-18

3. The use of a WLR technique to characterize voiding in 0.25 and 0.18 μm technologies for integrated circuits;1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296)

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