Optimization of Multiplexer Combination in RTL Logic Synthesis-Reference-Cited by-同舟云学术

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Optimization of Multiplexer Combination in RTL Logic Synthesis

Published:2023-05-08 Issue: Volume: Page:
ISSN:
Container-title:2023 International Symposium of Electronics Design Automation (ISEDA)
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Author:

Wang Zicheng¹,You Hailong¹,Wang Jie¹,Liu Meihua²,Su Yu³,Zhang Yong²

Affiliation:

1. School of Microelectronics, Xidian University,Xian,China

2. Institute of Advanced Computing and Digital Engineering, Shenzhen Institude of Advanced Technology Chinese Academy of Sciences,Shenzhen,China

3. Shenzhen GWX Technology Co.,Ltd.,Shenzhen,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10218344/10218369/10218464.pdf?arnumber=10218464

Reference11 articles.

1. Yosys manual[J];wolf;Retrieved,2021

2. Design Compiler Reference Manual Design Compiler Reference Manual[J];nurprasetyo;IEICE Transactions on Electronics,1998

3. Register binding and port assignment for multiplexer optimization

4. Optimization of multiplexer trees using modified truth table[C];pištck;2010 International Conference on Applied Electronics,0

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