IP Core Protection of Image Processing Filters with Multi-Level Encryption and Covert Steganographic Security Constraints-Reference-Cited by-同舟云学术

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IP Core Protection of Image Processing Filters with Multi-Level Encryption and Covert Steganographic Security Constraints

Published:2022-12 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Symposium on Smart Electronic Systems (iSES)
language:
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Author:

Anshul Aditya¹,Sengupta Anirban¹

Affiliation:

1. Computer Science and Engineering, Indian Institute of Technology,Indore,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10026847/10026888/10027040.pdf?arnumber=10027040

Reference12 articles.

1. High Energy Efficiency FPGA-Based Accelerator for Convolutional Neural Networks Using Weight Combination

2. An efficient reconfigurable hardware accelerator for convolutional neural networks

3. Behavioral synthesis techniques for intellectual property protection

4. CNN inference simulator for accurate and efficient accelerator design

5. A portable image processing accelerator using FPGA

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Hardware Security of Digital Image Filter IP Cores against Piracy using IP Seller’s Fingerprint Encrypted Amino Acid Biometric Sample;2023 Asian Hardware Oriented Security and Trust Symposium (AsianHOST);2023-12-13

2. Hardware Obfuscation Based Watermarking Technique for IPR Ownership Identification;International Journal of Reconfigurable Computing;2023-07-03

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